Static instruction scheduling for the HARP multiple-instruction-issue architecture
نویسندگان
چکیده
منابع مشابه
Static Instruction Scheduling
Dynamic Steering Logic is used. The evaluation is showed an average speedup of 35% over a conventional 8-way issue (4 int + 4 fp) machine. Altough integer programs seem not to have much parallelism , there is a growing number of integer applications with high ILP such as multimedia workloads (real time video and audio). Static vs Dynamic partitioning A static partitioning means that the compile...
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Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures. ILP processors put much more of a burden on compilers; without “heroic” compiling techniques, most such processors fall far short of their perfor...
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To achieve performance, Explicitly Parallel Instruction Computing (EPIC) systems take the responsibility of extracting instruction-level parallelism (ILP) from the hardware and give it to the compiler. They expose a large part of the hardware control at the conventional machine level. Dynamically Trace Scheduled VLIW (DTSVLIW) systems, on the other hand, leave the responsibility of extracting...
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ژورنال
عنوان ژورنال: Microprocessors and Microsystems
سال: 1993
ISSN: 0141-9331
DOI: 10.1016/0141-9331(93)90065-f